用verilog写8路频率不同流水灯? , 请问如何用verilog写8个流水灯

我用verilog写了一个简单的流水灯程序，只有几行代码，如下：module main(input clk,input rst,output reg [7:0] led );(*mark_debug = "true"*)reg [23:0] counter;always @(posedge clk) begin if(rst) begin counter <= 0;led <= 8'b00000001;

按键低电平有效，led灯低电平时亮。按键按下亮，松开灭。程序较简单，为组合逻辑电路，没有按键防抖功能。module led(led,key);input key;output led;reg led_out;always@(key)if(!key)led_out=1'b0;else led_out=1'b1;assign led=led_

你好，下面是对应的代码，另外时钟的频率不要太高否者实际的那个灯可能会看不来。module show(clk, reset, ledLight)input clk,reset;output [9:0] ledLight;reg [10:0] count ;always @(posdge clk or negedge reset)if (!reset)count =0;else if (count ==10)count =1;else count =

input rst;//system reset output [7:0] led; // 8bits led reg [7:0] led;reg [25:0] count;always @ (posedge clk ) begin if(rst || count[25]==1) begin count<=26'b0;end else count<=count+1;end always @ (posedge clk) begin if(rst)led<=8'b0000_0001;else begin

LED_Data_Port[7:0] <= 8'b0000_0100;//8'b1111_1111;4'd5:LED_Data_Port[7:0] <= 8'b0000_1000;//8'b0001_1000;4'd6:LED_Data_Port[7:0] <= 8'b0001_0000;//8'b0011_1100;4'd7:LED_Data_Port[7:0] <= 8'b0010_0000;//8'b0111_1110;4'd8:LED_Data_Port[7

这个其实可以用一个时钟来做8bit的计数器，8个bit的输出结果就是的8路流水灯。module ex(input clk , output reg [7:0]cnt ，input rst );always (posedge clk or neg edge rst )if (!rst )cnt <=0;else cnt <=cnt +1;endmodule

下面给一个 led 流水灯的实例：8个LED 从左到右依次点亮 module led ( input wire Clock, input wire RESET_N, output wire [7:0] LED ); // --- count 1s ---reg [27:0] cnt_1s;reg clk_1s_en; always @(posedge Clock or negedge RESET_N)begin if(!RES

用verilog写8路频率不同流水灯?

FPGA 和 C语言、单片机 没有绝对的关系。只能说有了单片机的基础，FPGA的外设更好应用。FPGA是面对硬件的语言，单片机是串行的。从头开始学，不要急。我建议你编写几个简单的例子。比如流水灯、定时器、倍频器等等。先找一块儿FPGA开发板吧。

module led8_display(clk,rst,comsel,en,play);input clk;input rst;input comsel;output[7:0] en;output[7:0] play;reg[30:0] count;reg[7:0] en;reg[7:0] play;always@(posedge clk or negedge rst)begin if(!rst)begin if(comsel)//共阳译码 begin count<=0;en<=1;play<=8'b

26采用VerilogHDL语言设计的频率计1.27简易频率计电路设计1.28简易频率计设计1.29电子数字钟1.30采用VerilogHDL语言设计的电子数字钟1.31采用VHDL语言设计的电子数字钟1.32电子时钟电路设计1.33计时器1.34波形发生器电路设计1.35LED数码管动态显示设计1.36流水灯电路设计1.37直流步进电机控制电路设计1

令clk为led流水灯(共计12个LED灯)的驱动时钟【要求低频，如1Hz】，rst为上升沿复位信号（异步）。则所实现的Verilog HDL代码部分如下：module led_run(clk,led,rst);input clk;//clk with low frequency like 1Hz input rst;//system reset signal output [11:0] led;//denotes 12 leds,reg [

module run_led(clk,rst,led); //module port input clk;//system clock input rst;//system reset output [7:0] led; // 8bits led reg [7:0] led;reg [25:0] count;always @ (posedge clk ) begin if(rst || count[25]==1) begin count<=26'b0;end else count<=count+1;e

用Verilog HDL语言设计流水灯实验程序

你好，下面是对应的代码，另外时钟的频率不要太高否者实际的那个灯可能会看不来。module show(clk, reset, ledLight)input clk,reset;output [9:0] ledLight;reg [10:0] count ;always @(posdge clk or negedge reset)if (!reset)count =0;else if (count ==10)count =1;else count =

这个其实可以用一个时钟来做8bit的计数器，8个bit的输出结果就是的8路流水灯。module ex(input clk , output reg [7:0]cnt ，input rst );always (posedge clk or neg edge rst )if (!rst )cnt <=0;else cnt <=cnt +1;endmodule

4'd3:LED_Data_Port[7:0] <= 8'b0000_0010;//8'b1110_0111;4'd4:LED_Data_Port[7:0] <= 8'b0000_0100;//8'b1111_1111;4'd5:LED_Data_Port[7:0] <= 8'b0000_1000;//8'b0001_1000;4'd6:LED_Data_Port[7:0] <= 8'b0001_0000;//8'b0011_1100;4'd7:LED_Data

下面给一个 led 流水灯的实例：8个LED 从左到右依次点亮 module led ( input wire Clock, input wire RESET_N, output wire [7:0] LED ); // --- count 1s ---reg [27:0] cnt_1s;reg clk_1s_en; always @(posedge Clock or negedge RESET_N)begin if(!RES

请问如何用verilog写8个流水灯

begin if(rst || count[25]==1) begin count<=26'b0;end else count<=count+1;end always @ (posedge clk) begin if(rst)led<=8'b0000_0001;else begin if(count[25]==1) begin led<=((led<<1)+1);end end end endmodule 这是我自己写的，实验正确符合楼主要求！嘿嘿。。。

你好，下面是对应的代码，另外时钟的频率不要太高否者实际的那个灯可能会看不来。module show(clk, reset, ledLight)input clk,reset;output [9:0] ledLight;reg [10:0] count ;always @(posdge clk or negedge reset)if (!reset)count =0;else if (count ==10)count =1;else count =

这个其实可以用一个时钟来做8bit的计数器，8个bit的输出结果就是的8路流水灯。module ex(input clk , output reg [7:0]cnt ，input rst );always (posedge clk or neg edge rst )if (!rst )cnt <=0;else cnt <=cnt +1;endmodule

LED_Data_Port[7:0] <= 8'b0000_1000;//8'b0001_1000;4'd6:LED_Data_Port[7:0] <= 8'b0001_0000;//8'b0011_1100;4'd7:LED_Data_Port[7:0] <= 8'b0010_0000;//8'b0111_1110;4'd8:LED_Data_Port[7:0] <= 8'b0100_0000;//8'b1111_1111;default:LED_Data_Port[7

// led 依次移位 endend 下面给一个 led 流水灯的实例：8个LED 从左到右依次点亮 module led ( input wire Clock, input wire RESET_N, output wire [7:0] LED ); // --- count 1s ---reg [27:0] cnt_1s;reg clk_1s_en; always @(posedge Clock or negedg

如何用verilog写8个流水灯

你好，下面是对应的代码，另外时钟的频率不要太高否者实际的那个灯可能会看不来。 module show(clk, reset, ledLight) input clk,reset; output [9:0] ledLight; reg [10:0] count ; always @(posdge clk or negedge reset) if (!reset) count =0; else if (count ==10) count =1; else count = count +1 assign ledLight[0] = (count ==1)? 1 :0; assign ledLight[1] = (count ==2)? 1 :0; assign ledLight[2] = (count ==3)? 1 :0; assign ledLight[3] = (count ==4)? 1 :0; assign ledLight[4] = (count ==5)? 1 :0; assign ledLight[5] = (count ==6)? 1 :0; assign ledLight[6] = (count ==7)? 1 :0; assign ledLight[7] = (count ==8)? 1 :0; assign ledLight[8] = (count ==9)? 1 :0; assign ledLight[9] = (count ==10)? 1 :0; endmodule
module ledwater(clk,led,s) input clk; input[1:0]s; output[7:0]led; reg [7:0] led=0; reg [1:0] olds=0; always@(posedge clk) olds<=s; always@(posedge clk) if (olds^s) case (s) 2'b00: led<=1; //*a 2'b01: led<=1; 2'b10: led<=8'b1010_1010; 2'b11: led<=8'b0000_0111; endcase else case (s) 2'b00: led<={led[6:0],led[7]};//*b 2'b01: led<={led[0], led[7:1]}; 2'b10: led<=~led; 2'b11: led<={led[6:0],led[7]}; endcaseendmodule//第一种：一个灯亮，从右往左逐个移动，并循环//第二种：一个灯亮，从左往右逐个移动，并循环//第三种：一个间一个灯亮，并交替循环//第四种：三个灯亮，从右往左逐个移动，并循环//当然可以再多一些花样：//如：灯从右往左逐步点亮// *a改为: led<=1;// *b改为: led<= (&led)? 1: {led[6:0],1'b1};
module first_soft (clk, rst, led);//port input clk, rst; output [7:0] led; reg [7:0] led; reg [24:0] count;//计数器 reg [24:0] speed;//速度 reg [3:0] state;//状态,[3]=1:正转;[3]=0:翻转;{2,0}速度 always @(posedge clk or negedge rst)//自动变频流水灯 if (!rst) begin statelt;=4;d0; ledlt;=8;b00000001; countlt;=25;d0; speedlt;=25;d20000000; end else begin countlt;=count+1;b1; if (count==speed) begin countlt;=25;d0;//计数器复位 if (state[3]==0)//转移发光二极管 begin ledlt;=ledlt;lt;1;b1; if (led==8;b01000000) state[3]lt;=1;b1; end else begin ledlt;=led;;1;b1; if (led==8;b00000010) begin case (state[2:0]) 3;b000: begin speedlt;=25;d10000000; state[3:0]lt;=4;b0001; end 3;b001: begin speedlt;=25;d5000000; state[3:0]lt;=4;b0010; end 3;b010: begin speedlt;=25;d2500000; state[3:0]lt;=4;b0011; end 3;b011: begin speedlt;=25;d1200000; state[3:0]lt;=4;b0100; end 3;b100: begin speedlt;=25;d2500000; state[3:0]lt;=4;b0101; end 3;b101: begin speedlt;=25;d5000000; state[3:0]lt;=4;b0110; end 3;b110: begin speedlt;=25;d10000000; state[3:0]lt;=4;b0111; end 3;b111: begin speedlt;=25;d20000000; state[3:0]lt;=4;b0000; end default: begin speedlt;=25;d20000000; state[3:0]lt;=4;b0000; end endcase end end end end endmodule
你好，下面是对应的代码，另外时钟的频率不要太高否者实际的那个灯可能会看不来。 module show(clk, reset, ledLight) input clk,reset; output [9:0] ledLight; reg [10:0] count ; always @(posdge clk or negedge reset) if (!reset) count =0; else if (count ==10) count =1; else count = count +1 assign ledLight[0] = (count ==1)? 1 :0; assign ledLight[1] = (count ==2)? 1 :0; assign ledLight[2] = (count ==3)? 1 :0; assign ledLight[3] = (count ==4)? 1 :0; assign ledLight[4] = (count ==5)? 1 :0; assign ledLight[5] = (count ==6)? 1 :0; assign ledLight[6] = (count ==7)? 1 :0; assign ledLight[7] = (count ==8)? 1 :0; assign ledLight[8] = (count ==9)? 1 :0; assign ledLight[9] = (count ==10)? 1 :0; endmodule
module clk_div(clk,out1,out2); input clk; output out1,out2; reg out1,out2; reg [31:0]cnt1,cnt2; always @(posedge clk)begin//50MHz分频计数 if(cnt1<32'd24999999) cnt1 <=cnt1 + 32'd1; else cnt1 <=32'd0; end always @(posedge clk)//分频后的半周期反转 if(cnt1 == 0) out1<=~out1; always @(posedge clk)begin//5MHz分频计数 if(cnt2<32'd4999999) cnt2 <=cnt2 + 32'd1; else cnt2 <=32'd0; end always @(posedge clk)//20%占空比 if(cnt2 == 32'd999999) out2<=0; else if(cnt2 == 32'd4999999) out2<=1; endmodule
周期=1/20秒 时钟晶振选用50mhz的话，0.05秒就需要clk跑5*0.01*50*10^6= 2 500 000 module led; input clk,rst; output ledcon; reg [3:0] led; //led开关锁存位 reg d1,d2,d3,d4;//四个灯开关 reg [21:0] cnt_5; //0.05秒计数器 reg count; // 数满标志位 always @(posedge clk or negedge rst) if (!rst) cnt_5<=22'd0; else if(cnt_5==22'd2500000) cnt_5<=22'd0; //数满归零 else cnt_5<=cnt_5+1'b1; always @(posedge clk or negedge rst)) if(!rst) count<=1'b0; else if (cnt_5==22'd2500000) count<=1'b1; 我擦。。剩下我不写了。你查查网上资料吧。 就是每数满时间就依次轮换打开d1--d4开关并且关闭前一个。 ledcon用连续赋值